The present invention relates to a turn off type semiconductor device and more particularly to a turn off type semiconductor device suitable for a high speed switching operation and an increase in a controllable current, a method of the same and the power conversion apparatus employing the same.
By the request of heightening an operating frequency an increasing a power in a power conversion apparatus such as an inverter, it is desired to develop a switching device which is capable of cutting off a large current at a high speed. As a typical switching device, there is given a GTO (gate turn off type) thyristor which is capable of turning on or off by receiving a gate signal. In general, the magnitude of a controllable current of the GTO thyristor is in inverse proportion to a gate impedance (r.sub.G) and is in proportion to a reverse breakdown voltage (BV.sub.GK) across a gate and a cathode. In other words, if r.sub.G is decreased to heighten BV.sub.GK, it is possible to increase the controllable current. Moreover, increasing r.sub.G to heighten BV.sub.GK allows carriers in a base layer to be extracted at a high speed, and therefore, it is none other than the operation capable of turning off at a high speed. If a realistic device structure is considered, there is a limit in increasing BV.sub.GK from a relation to and on voltage and turn on characteristics. In this connection, the most important point for making an operation speed higher and making a current larger is that r.sub.G is decreased to the limit.
In order to solve the above problem, as disclosed in JP-A-62-147769 (the term JP-A used herein means that the patent application was laid open to public inspection but has not been examined), there has been proposed a GTO thyristor in which a low impurity concentrated p-type base layer is provided in a p-type base layer at the side of an n-type emitter layer, and a high impurity concentrated p-type layer used for gate contact is provided so as to be in contact with a highest impurity concentrated region of said p-type base layer. With this thyristor, a gate impedance is intended to be reduced by the so-called buried p.sup.+ -type gate structure in which a high impurity concentrated p-type layer is buried in a low impurity concentrated p type base layer under an n-type emitter layer using the epitaxial growth technique.